Performance Benefits of Special-Purpose Instructions in the CSI Architecture

The Complex Streamed Instruction Set (CSI) architecture was proposed in order to overcome the limitations of existing multimedia-oriented ISA extensions, such as Intel’s MMX and SSE. One of the main limitations is the large amount of instructions which has to be executed. In CSI, instructions operate on data streams of arbitrarylength, which allows to dramatically reduce the instruction counts for the kernels with sufficient amount of data-level parallelism. Previously, we have shown that CSI provides impressive performance improvements for several important multimedia kernels and applications. In these experiments the kernels were coded using elementary arithmetic CSI instructions such as addition, multiplication, etc. Many kernels, however, perform more complex operations and, thus, need to be translated to multiple elementary CSI instructions. For some kernels, CSI provides special-purpose instructions that collapse several elementary operations in a single complex one and thereby achieve an additional reduction of the number of executed instructions. In this paper we study the performance provided by an example of such an instruction. Using the SimpleScalar simulator, we evaluate performance of the superscalar CPU augmented with the CSI execution unit on the Paeth prediction kernel of the image encoder/decoder for the PNG image compression standard. Simulation results show that the kernel-level performance of the 4-way superscalar CPU augmented with the CSI execution unit improves by the factor of 12.9x when this kernel is implemented using the special-purpose CSI instruction instead of the elementary ones. Keywords— Processor Architecture, Multimedia ISA Extensions, Data-level parallelism